1. Field of the Invention
The present invention relates to a memory circuit, and particularly to a memory circuit that can be capable of being quickly written in data.
2. Description of the Prior Art
As shown in FIG. 1, when an application unit (not shown in FIG. 1) coupled to a memory circuit needs to write data into memory cells MC1-MCM of a segment MS1 of a bank B1 of the memory circuit, a controller (not shown in FIG. 1) of the memory circuit first enables an active command ACT corresponding to an address of the bank B1 and a word line WL1. When the controller enables the active command ACT, a word line switch corresponding to the word line WL1 can be turned on according to the active command ACT. After the controller enables the active command ACT, the controller enables a write command WRC corresponding to the address of the bank B1 and an address of the segment MS1. When the controller enables the write command WRC, bit switches corresponding to the bit lines BL1-BLM of the segment MS1 can be turned on according to the write command WRC. Therefore, after the bit switches corresponding to the bit lines BL1-BLM are turned on, the data can be written into the memory cells MC1-MCM in turn through data lines (not shown in FIG. 1) of the memory circuit, the bit lines BL1-BLM, and a sense amplifier SA. In addition, as shown in FIG. 1, WL2-WLN represent word lines, MS2 represents a segment, M, N are integers greater than 1, and all segments of the memory circuit share the sense amplifier SA.
As shown in FIG. 2, because the bit switches corresponding to the bit lines BL1-BLM of the segment MS1 are turned on according to the write command WRC, the write command WRC needs to include M clock signals making the bit switches corresponding to the bit lines BL1-BLM be turned on after the active command ACT, wherein the controller can enable a pre-charge command PREC corresponding to the address of the bank B1 after the write command WRC, and FIG. 2 illustrates a timing of the active command ACT, the write command WRC, and the pre-charge command PREC enabled by the controller.
As shown in FIG. 2, because the write command WRC includes the M clock signals, time for writing the data into the memory cells MC1-MCM at least includes time of the M clock signals and time of the active command ACT, that is, it will take much time to write the data into the memory cells MC1-MCM.